1. Field of the Invention
The present invention relates generally to a semiconductor device. More particularly, the invention relates to a metal input/output (I/O) ring structure for a semiconductor device.
This application claims the priority of Korean Patent Application No. 10-2004-0078547 filed on Oct. 2, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
As process technology for semiconductor devices continues to improve, the operating speed and the degree of integration for the devices increases accordingly. Due to a continuing increase in the size of semiconductor chips, the number of pads used in semiconductor chips can range from several hundreds to more than one thousand. However, in order to minimize power consumption, the typical size of a power source supplied to the chips tends to become smaller and smaller. As a result, the typical noise margin for semiconductor chips is continually reduced, thereby deteriorating the overall performance of systems using the semiconductor chips.
Effective noise reduction can cause a dramatic improvement in the performance of a semiconductor system. For example, simultaneous switching noise (SSN) resulting from a disrupted power distribution in a package and/or a printed circuit board (PCB) of a semiconductor system can be reduced by including several power/ground pins in the system and making sure that the power/ground pins are adequately spread out. Unfortunately, reducing SSN in this way causes a problem in that it tends to increase chip size and package manufacturing cost. As a result, SSN is often reduced by a method involving an on-chip decoupling capacitance.
A conventional technique for providing on-chip decoupling capacitance has been realized with metal oxide semiconductor (MOS) transistors. Unfortunately, using this type of decoupling capacitance tends to have a negative effect on system performance due to associated leakage currents. Also, it is extremely difficult to manufacture a sufficiently large decoupling capacitance due to limited on-chip space. In addition, in cases where a conventional metal I/O ring is used, although the metal element used for the power supply generally has a width of at least 100 μm, only a capacitance between adjacent metal rings is used for a decoupling capacitance. Hence it is difficult to provide a decoupling capacitance of more than several picofarads. Finally, it is difficult to make adjustments to the structure of the metal I/O ring to obtain a desired capacitance.
FIG. 1 is a schematic view of a conventional I/O cell. Referring to FIG. 1, an I/O cell is constructed to have a metal ring structure providing a steady power/ground supply. In FIG. 1, metal lines for power cells and metal lines for ground (GND) cells are alternately arranged in a horizontal direction, and the power and ground cells are interconnected to form a ring structure surrounding a semiconductor device.
FIG. 2 is a cross-sectional view of a metal ring structure for a conventional I/O cell. Referring to FIG. 2, a conventional metal I/O ring structure comprises a plurality of power cells 22 and 24 and a plurality of ground cells 21 and 23 alternately arranged along a horizontal direction, with power cells and ground cells adjacent to each other. The power cells and the ground cells are isolated from each other by an electrical insulator interposed therebetween and hence a decoupling capacitance is formed between horizontally adjacent ground and power cells.
The power cells and the ground cells each have a plurality of vertically-layered metal lines connected by a plurality of vias 26 interposed therebetween as shown in FIG. 2. Each of the metal lines within a cell has the same voltage. For example, in a power cell, the plurality of metal lines is connected to a power source voltage, and in a ground cell, the plurality of metal lines is connected to ground.
In FIG. 2, ground cell 21 comprises a ground metal line M6 and a ground metal line M5 located below metal line M6. Ground metal lines M5 and M6 are connected by vias 26 interposed therebetween. Ground cell 21 further comprises a ground metal line M4 located below metal line M5 and a ground metal line M3 located below ground metal line M4. Ground metal lines M5 and M4 and M4 and M3 are respectively connected by vias 26 interposed therebetween. Power cell 22 also comprises power metal lines M6, M5, M4, and M3, where power metal line M5 is located below power metal line M6, power metal line M4 is located below power metal line M5, and power metal line M3 is located below power metal line M4. Each of power metal lines M6, M5, M4, and M3 is connected to vertically adjacent power metal lines by vias 26 interposed therebetween.
A capacitor 25 is placed between ground metal line M3 and power metal line M3 to provide a decoupling capacitance.
FIG. 3 is a top view of the metal ring structure of the conventional I/O cell shown in FIG. 2. Referring to FIG. 3, ground metal lines and power metal lines are alternately arranged, and vertically adjacent layered metal lines are connected by vias 26 interposed therebetween.
As shown in FIGS. 2 and 3, in a conventional metal I/O ring structure, the metal layers of a ground or power cell are vertically connected by vias interposed therebetween and a capacitor is placed between horizontally adjacent ground and power metal lines of the same layer in order to provide a decoupling capacitance. As previously mentioned, one of the shortcomings of the conventional metal I/O ring structure is that the capacitor does not exceed several picofarads (pfs).